DocumentCode :
642803
Title :
Dynamic hardware specialization-using moore´s bounty without burning the chip down
Author :
Sankaralingam, K.
Author_Institution :
Univ. of Wisconsin-Madison, Madison, WI, USA
fYear :
2013
fDate :
Sept. 29 2013-Oct. 4 2013
Firstpage :
1
Lastpage :
1
Abstract :
Summary form only given. The era of faster, smaller, greener (more power efficient) transistors in every successive generation appears to be dead. Due to slowing voltage scaling power has becoming a primary design constraint. Using conventional microprocessor techniques does not provide performance improvements without excessive power consumption. Instead, processor architects and microarchitects are going to be partially burdened with power-efficiently and energy-efficiently improving performance with technology scaling providing density improvements “alone”. The DySER project investigates ways for dynamically specializing datapaths to energy-efficiently improve performance. DySER attempts to provide a truly general purpose accelerator, avoiding radical changes to software development, ISA, or microarchitecture. The DySER accelerator is based on three principles: i) Exploit frequently executed, specializable code regions. ii) Dynamically configure the DySER accelerator hardware for particular regions. iii) Integrate the accelerator tightly, but non-intrusively, to a processor pipeline.We have completed a full prototype implementation of DySER integrated into the OpenSPARC processor (called SPARCDySER), a co-designed compiler in LLVM, and a detailed performance evaluation on an FPGA system, which runs an Ubuntu Linux distribution and full applications. Through the prototype, we evaluate the fundamental principles of DySER acceleration, namely: exploiting specializable regions, dynamically specializing hardware, and tight processor integration. To this end, we explore the accelerator´s performance, power, and area, and consider comparisons to state-of-the-art microprocessors using energy/performance frontier analysis of both the prototype and simulated DySERaccelerated cores. Compared to the OpenSPARC processor, DySER provides 6.2X performance improvements and 4X energy reduction. DySER´s approach of dynamic specialization is a promising way to add- ess the imminent power challenges.
Keywords :
Linux; energy conservation; field programmable gate arrays; formal specification; power aware computing; program compilers; DySER accelerator; FPGA system; Moore bounty; OpenSPARC processor compiler; Ubuntu Linux distribution; conventional microprocessor techniques; datapaths specalization; design constraint; dynamic hardware specialization; dynamically specializing hardware principle; exploiting specializable regions principle; field programmable gate array; general purpose accelerator; power consumption; processor integration principle; software development; transistors; voltage scaling power; Acceleration; Educational institutions; Green products; Hardware; Power demand; Prototypes; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2013 International Conference on
Conference_Location :
Montreal, QC
Type :
conf
DOI :
10.1109/CASES.2013.6662522
Filename :
6662522
Link To Document :
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