Title :
A complete solution for Board-Level Signal Integrity Analysis Using IBIS Models
Author :
Shariati, Zahra ; Masoumi, Nasser ; Mehri, Milad
Author_Institution :
Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
Abstract :
In this work the IBIS is employed to estimate the adverse effects of package wheresome modifications in its representation are proposed. IBIS is a standard file type which is widely popular in system design level. Many vendors, designers, and circuit simulators produce, use, and accept this standard nowadays. It represents the behavior of the I/O buffer of digital circuit considering their package parasitic effects. Our modifications on IBIS give rise to be better understanding of the package and digital I/O. The different conventional packages are tested considering wire connection between two chips. The effects of package and I/O, in companion with wire delay, overshoot, and undershoot on signal transition, are studied. The parasitic adverse effect of package can be as high as 41% for propagation delay and 38% for overshoot voltage.
Keywords :
digital integrated circuits; integrated circuit packaging; IBIS models; board level signal integrity analysis; digital circuit; overshoot; package parasitic effects; signal transition; standard file type; system design level; undershoot; wire delay; Data models; Educational institutions; Integrated circuit modeling; Propagation delay; RLC circuits; Voltage measurement; Wires; Delay; IBIS Model; PCB Traces; Package Parasitic;
Conference_Titel :
Microwave Symposium (MMS), 2013 13th Mediterranean
Conference_Location :
Saida
DOI :
10.1109/MMS.2013.6663098
