Compression of LLR messages of an Elementary Check Node processor of a Non-Binary LDPC decoder

Non-Binary LDPC codes are nowadays considered as a potential competitor of both binary LDPC and convolutional Turbo Codes, mainly when codes with short and moderate codeword lengths are used. The decoding process of these codes suffers from a high computational complexity which necessitates a high memory requirements to store the intrinsic and extrinsic Likelihood Ratio (LLR) messages. This paper addresses the compression of the binary words bearing the LLR values from 6 to 3 bits by storing the difference of two consecutive LLRs instead of the entire values. A new architecture of the Elementary Check Node is then proposed. The Monte Carlo simulation results show that the proposed compression scheme does not introduce any performance loss of the code.