System level hardware testing of a high speed MAP decoder implemented on FPGA

In this paper, a systematic approach of hardware prototyping and testing a digital design of maximum-a-posteriori (MAP) decoder for a communication system is presented. A MAP decoder architecture for the high speed application is chosen for the implementation on field-programmable-gate-array (FPGA) board. The test-setup of a communication system with binary-phase-shift-keying (BPSK) modulation scheme in an additive-white-Gaussian-noise (AWGN) channel environment is designed to verify the hardware prototype of the decoder. Subsequently, the integration of hardware prototype with integrated logic analyzer core using control cores and parallel cables are presented. The hardware prototype of MAP decoder implemented on FPGA has achieved a biterror-rate (BER) of 10^-4 at an E_b/N₀ of 4.75 dB and has a degraded performance as compared to simulated MAP algorithm by approximately 0.2 dB. In addition, the implemented MAP decoder has a maximum achievable frequency of 411 MHz.