Analysis of the IEEE 802.15.4a UWB PHY layer for optimizing the power consumption of the transmitter

This paper presents an analysis of the power consumption of the UWB PHY layer of the IEEE 802.15.4a standard. This work focuses on the transmitter PHY layer implementation. The influence of the different modes settings on the power consumption is investigated. The considered implementations use an FPGA coupled with an UWB pulse generator implemented in an ASIC. The first PHY layer implementation is fully integrated in the FPGA. The consumption study reveals that the system consumption is reduced with the Mean PRF of 3.9 MHz due to the lower number of emitted pulses. The study also shows that the highest power consumption is due to the 499.2 MHz clock. The second implementation proposes to move the 499.2 MHz clock into the ASIC to reduce its consumption. For the mandatory data rate and the 3.9 MHz Mean PRF, this technique reduces the energy by emitted bit from 2574 pJ to 727 pJ.