Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology

This article proposed an area-efficient carry select adder by sharing the common Boolean logic term. Representation of the circuit in summation operation need one XOR gate and one Inverter, while carry out can be represented using one AND gate and an inverter. Using the multiplexer, we are able to select the correct output results according to the carry input signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960 and the carry select adder performs with a faster speed as compare to the carry ripple adder. Two different design styles using one multiplexer and two multiplexers has also been considered in terms of number of transistors, average power consumption, propagation delay at sum and at carry output.