Implementation of One Level 2D DWT Using Multiplier Less Modified Flipping Architecture

This paper presents a novel architecture for the implementation of one level 2D DWT. The architecture is designed by using shifters and adders without using multipliers. The structure is designed for modified flipping based DWT. The System On Programmable Chip approach (SPOC) is adopted for the implementation of one level 2D DWT on Alter a Field Programmable Gate Array CYCLONE II EP2C35F672C6 kits with NIOS-II soft-core processor. From the implementation results, it is verified that, the proposed multiplier less modified flipping structure operated with higher speed by 7.39% and reduces the logical elements by 22.98% compared with modified flipping structure. The power dissipation is also reduced by 3.3% compared to modified flipping structure.