A 128/512/1024/2048-point pipeline FFT/IFFT architecture for mobile WiMAX

This paper presents a low-power radix-2 pipeline FFT architecture with 128/512/1024/2048 points for mobile WiMAX. A single-path delay feedback style was adopted as the hardware architecture of the proposed design. For the embedded memory, the proposed design adopts low-power single-port register files to implement delay-line buffers, which can obtain an efficient power reduction. Finally, the proposed design requires approximately 140K gates, and its power consumption is approximately 18 mW at 20 MHz.