• DocumentCode
    644277
  • Title

    Design principles for packet parsers

  • Author

    Gibb, Glen ; Varghese, George ; Horowitz, Mark ; McKeown, Nick

  • Author_Institution
    Stanford University, USA
  • fYear
    2013
  • fDate
    21-22 Oct. 2013
  • Firstpage
    13
  • Lastpage
    24
  • Abstract
    All network devices must parse packet headers to decide how packets should be processed. A 64 × 10Gb/s Ethernet switch must parse one billion packets per second to extract fields used in forwarding decisions. Although a necessary part of all switch hardware, very little has been written on parser design and the trade-offs between different designs. Is it better to design one fast parser, or several slow parsers? What is the cost of making the parser reconfigurable in the field? What design decisions most impact power and area? In this paper, we describe trade-offs in parser design, identify design principles for switch and router designers, and describe a parser generator that outputs synthesizable Verilog that is available for download. We show that i) packet parsers today occupy about 1–2% of the chip, and ii) while future packet parsers will need to be programmable, this only doubles the (already small) area needed.
  • Keywords
    Abstracts; Application specific integrated circuits; Data mining; Multiprotocol label switching; Program processors; Random access memory; Switches; Design principles; Parsing; Reconfigurable parsers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Architectures for Networking and Communications Systems (ANCS), 2013 ACM/IEEE Symposium on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    978-1-4799-1640-5
  • Type

    conf

  • DOI
    10.1109/ANCS.2013.6665172
  • Filename
    6665172