• DocumentCode
    644394
  • Title

    High-Speed Multicast Scheduling for All-Optical Packet Switches

  • Author

    Zhiyang Guo ; Yuanyuan Yang

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Stony Brook Univ., Stony Brook, NY, USA
  • fYear
    2013
  • fDate
    17-19 July 2013
  • Firstpage
    156
  • Lastpage
    165
  • Abstract
    In this paper, we study multicast scheduling in all-optical packet switches. We first propose a novel optical buffer called multicast-enabled Fiber-Delay-Lines (M-FDLs), which can provide flexible delay for copies of multicast packets using only a small number of FDL segments. We then present a Delay-Guaranteed Multicast Scheduling (DGMS) algorithm that considers the schedule of each arriving packet for multiple time slots. We show that DGMS has several desirable features, such as guaranteed delay upper bound and adaptivity to transmission requirements. To relax the time constraint of DGMS, we further propose a parallel and pipeline architecture for DGMS that distributes the scheduling task to multiple pipelined processing stages, with N processors in each stage, where N is the switch size. Finally, by using a simple combination logic circuit, we show that each processor can finish the scheduling for one time slot in O(1) time. The performance of DGMS is tested extensively against statistical traffic models and real Internet traffic, and the results show that the proposed DGMS algorithm can achieve ultra-low average packet delay with minimum packet drop ratio.
  • Keywords
    combinational circuits; communication complexity; multicast communication; optical switches; packet switching; parallel architectures; pipeline processing; scheduling; telecommunication computing; DGMS algorithm; FDL segments; M-FDLs; all-optical packet switches; combination logic circuit; delay-guaranteed multicast scheduling algorithm; guaranteed delay upper bound; high-speed multicast scheduling; multicast packets; multicast-enabled fiber-delay-lines; optical buffer; parallel architecture; pipeline architecture; pipelined processing stages; time slots; transmission requirements; Delays; Optical buffering; Optical packet switching; Optical switches; Program processors; Scheduling; Vectors; Optical packet switching; delay guaranteed; hardware implementation; multicast scheduling; optical buffer; parallel; pipeline;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networking, Architecture and Storage (NAS), 2013 IEEE Eighth International Conference on
  • Conference_Location
    Xi´an
  • Type

    conf

  • DOI
    10.1109/NAS.2013.26
  • Filename
    6665358