Title :
A novel fast modular multiplier architecture for 8,192-bit RSA cryposystem
Author :
Wei Wang ; Xinming Huang
Author_Institution :
Dept. of Electrial & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA
Abstract :
Modular multiplication is the most crucial component in RSA cryptosystem. In this paper, we present a new modular multiplication architecture using the Strassen multiplication algorithm and Montgomery reduction. The architecture is different from the interleaved version of Montgomery multiplication traditionally used in RSA design. By selecting different bases of 16 or 24 bits, it could perform 8,192-bit or 12,288-bit modular multiplication. The design was synthesized on the Altera´s Stratix-V FPGA using Quartus II. It performs one modular multiplication in 2,030 cycles. When operating at 209 MHz, the execution time for an 8K- or 12K-bit modular multiplication is about 9.7 μs.
Keywords :
cryptography; digital arithmetic; field programmable gate arrays; 8,192-bit RSA cryposystem; Altera Stratix-V FPGA; Montgomery reduction; Quartus II; RSA design; Strassen multiplication algorithm; fast modular multiplier architecture; modular multiplication architecture; Algorithm design and analysis; Computer architecture; Field programmable gate arrays; Hardware; Public key cryptography; Throughput; FPGA; Montgomery Algorithm; RSA; Strassen Multiplication;
Conference_Titel :
High Performance Extreme Computing Conference (HPEC), 2013 IEEE
Conference_Location :
Waltham, MA
Print_ISBN :
978-1-4799-1364-0
DOI :
10.1109/HPEC.2013.6670320
