Vendor agnostic, high performance, double precision Floating Point division for FPGAs

Double precision Floating Point (FP) arithmetic operations are widely used in many applications such as image and signal processing and scientific computing. Field Programmable Gate Arrays (FPGAs) are a popular platform for accelerating such applications due to their relative high performance, flexibility and low power consumption compared to general purpose processors and GPUs. Increasingly scientists are interested in double precision FP operations implemented on FPGAs. FP division and square root are much more difficult to implement than addition and multiplication. In this paper we focus on a fast divider design for double precision floating point that makes efficient use of FPGA resources including embedded multipliers. The design is table based; we compare it to iterative and digit recurrence implementations. Our division implementation targets performance with balanced latency and high clock frequency. Our design has been implemented on both Xilinx and Altera FPGAs. The table based double precision floating point divider provides a good tradeoff between area and performance and produces good results when targeting both Xilinx and Altera FPGAs.