A high-voltage driving 60 GHz power amplifier with Psat of 13 dBm and PAE of 9.1% in 90 nm CMOS for IEEE 802.11ad communication systems

A high-voltage (3 V) driving 60 GHz power amplifier (PA) for direct-conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low-impedance inter-stage matching, followed by a common-source output stage. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner (IL=0.536 dB @60 GHz) are used. This in turn results in further P_sat and PAE enhancement. The PA consumes 176.2 mW and achieves power gain (S₂₁) of 17.9±3.7 dB, input-port input reflection coefficient (S₁₁) of -5.8~ -7.3 dB, output-port input reflection coefficient (S₂₂) of -10.4~ -26.3 dB, and reverse isolation (S₁₂) of -56.4~ -81.7 dB for frequencies 50-60 GHz. In addition, for frequencies 50-60 GHz, the PA achieves output 1-dB compression point (OP_1dB) of 6.6~7.8 dBm, P_sat of 10.6~13 dBm and maximum PAE of 9.1%, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60-GHz short-range communication system applications.