Comparative study of transmission lines design for 2.5D silicon interposer

In this paper, we present the results of a comparative study performed on six commonly used on-chip differential trace designs in newly emerging 2.5D silicon interposer with high-speed signalling. A generic equivalent circuit model is proposed based on physical geometry. The circuit model is compatible for all the trace structures studied. Impacts of circuit elements in the model are explained theoretically with a physics-based design optimization method. Tradeoff between channel performance and I/O numbers for various trace designs are also discussed in the paper. Unequalized eye of a 10Gb/s simulated transmitter with the best selected on-chip transmission lines geometries showing the possibility to achieve successful communication for 10 Gb/s signal through 40-mm interconnects on the silicon interposer.