System level simulation solutions for high-speed channels - Package and PCB interface

Package and PCB co-simulation is common in system level companies for the prediction of high-speed channel performance. In recent times, chip companies have been paying closer attention to package and PCB co-simulations in order to guarantee the performances of these chips at the system level. However, full-wave package and PCB co-simulation can be challenging: if the package and PCB are modeled together, the co-simulation is limited by either available computational resource, due to the extremely large memory consumption, or by affordable simulation time. The current, widely adopted method in industry, for PCB and package co-simulation, is to model them separately. There has been little investigation of where to separate/segment the PCB and package and build a reference plane. The reference plane is critical to the simulation results of the entire channel. It is recognized that a TEM wave is required at the reference plane so that the current and voltage are well defined. It can be difficult to tell if a TEM wave is established at the reference plane and if it is not, what is the solution? This paper investigates these details and will give a more general solution for PCB and package co-simulation based on the consideration of accuracy and efficiency.