Investigation of power & ground co-reference for high-speed signal in package design

With silicon process technology advanced to 20 nm node and beyond, die size is continuously shrinking. Package cost is very sensitive to the total cost of an entire chip/ASIC (Application-Specific Integrated Circuit). To reduce package cost, either the package layer count needs to be reduced or the package size needs to be decreased. For a given chip/ASIC design, its high-speed IO (Input Output) pin numbers are fixed in order to meet a certain functional specification, and associated power pins are optimized to guarantee the IO performance. If some of the power pins can be used as references for high-speed IOs, a same die can sit on a small package or a same package can accommodate a die with more high-speed IO pins, which equivalently results the package cost reduction. This motivates the investigation on power and ground co-reference design for highs-speed IOs not only on the concern of cost reduction but also the design insights. In this paper, a production based package with pure ground as reference is studied. A power and ground co-reference design is formed by changing six ground pins from the production package to power pins in test package. The performance of high-speed IOs is compared between pure ground reference design and the power and ground co-reference design. Discussions and conclusions are followed by the comparison, and further study is proposed at the end of the paper.