Real-time distance protective relay on FPGA

The paper proposes a real-time hardware digital distance protective relay. Taking advantage of inherent hardwired architecture of the Field Programmable Gate Array (FPGA), the proposed hardware distance relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in textual VHDL language. This hardware distance relay is tested in real-time by feeding it with generated faulted current and voltage data for typical faults, and the relay response was recorded. The results demonstrate the effectiveness of the hardware distance relay.