An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library

Pulse-triggered flip-flops are candidates to improve pipeline speed, although flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Pulse-triggered flip-flops usually have specific structures and transistor sizes to optimize performance. The topology, transistor size, and threshold voltage of the flip-flop make the timing characteristics sensitive to the supply voltage. The transparent windows generated and required in a pulse-triggered flip-flop may have mismatch under supply voltage scaling, which is likely to result in functional and system timing failures. Therefore, this brief proposes an adaptive pulse-generating method to fit the transparent window required in situ. Process variations and intrinsic transistor driving-strength mismatches are considered. The proposed structure improves the robustness of pulse-triggered flip-flops and promises this high-speed clocked element for wide-voltage-range operations. A normalized timing metric is also introduced to characterize flip-flops and help timing tradeoffs in wide-voltage-range operations.