A hardware-based approach for saving cache energy in multicore simulation of power systems

Due to the wide spread use of computing systems such as multicore servers, laptops and iPods, their contribution in national power consumption has significantly increased. Further, driven by the recent trends in chip fabrication and transistor scaling, the size and power consumption of caches has also increased and hence, they contribute significantly to overall processor power consumption. In this paper, we present an approach for reducing cache energy consumption in computationally-intensive, dynamic simulation of power systems. We leverage the intra-program and inter-program variation in cache demands during analysis of different contingencies and use drowsy cache technique to turn off unused cache to save leakage energy. We simulate several contingencies of different power systems using dual-core and quadcore configurations in a computer architecture simulator. The simulation results have shown that our approach is effective in saving cache leakage energy and does not harm the performance.