Title :
A 6-bit CMOS inverter based pseudo-flash ADC with low power consumption
Author :
Morozov, D.V. ; Pilipko, M.M. ; Piatak, I.M.
Author_Institution :
St.-Petersburg State Polytech. Univ., St. Petersburg, Russia
Abstract :
A 6-bit pseudo-flash ADC is presented. CMOS inverters are used instead of a reference ladder of well matched resistors and comparators to reduce power consumption of the ADC. Influence of temperature and technology process variations on the inverters threshold voltages is considered. The results of ADC computer simulation in UMC 180 nm CMOS technology showed that sampling rate is 100 Ms/s, power consumption is 820 uW. The ADC occupies 60×120 um2.
Keywords :
CMOS logic circuits; analogue-digital conversion; comparators (circuits); ladder networks; logic gates; resistors; ADC computer simulation; CMOS inverter-based pseudoflash ADC; UMC CMOS technology; comparators; inverter threshold voltages; power 820 muW; power consumption reduction; reference ladder; sampling rate; size 180 nm; technology process variation; well-matched resistors;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673079
