Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration

Design automation tool to perform conversion of FPGA configuration to EDIF and VHDL descriptions is proposed in this paper. From a Xilinx FPGA Spartan3 bitstream given in the XDL (Xilinx Design Language) format file, the description in EDIF or VHDL is generated. The proposed tool is a link between design platforms of FPGA and ASIC has made it easier for designers to test out a complex ASIC design on a single FPGA.