Title :
Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration
Author :
Cheremisinov, D.I.
Author_Institution :
United Inst. of Inf. Problems (UIIP), Minsk, Belarus
Abstract :
Design automation tool to perform conversion of FPGA configuration to EDIF and VHDL descriptions is proposed in this paper. From a Xilinx FPGA Spartan3 bitstream given in the XDL (Xilinx Design Language) format file, the description in EDIF or VHDL is generated. The proposed tool is a link between design platforms of FPGA and ASIC has made it easier for designers to test out a complex ASIC design on a single FPGA.
Keywords :
application specific integrated circuits; automatic testing; field programmable gate arrays; hardware description languages; integrated circuit design; ASIC design; EDIF descriptions; FPGA configuration extraction; VHDL descriptions; XDL format file; Xilinx FPGA Spartan3 bitstream; Xilinx design language; design automation tool;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673098
