Low-power design of combinational CMOS networks

An approach to logic synthesis using CMOC element library is suggested, which allows to minimize the area and the average value of the dissipated power of microcircuit implemented on CMOC VLSI chip. The case of synthesis of combinational CMOC networks is considered when key schematic solutions, such as clock frequency and supply voltage, are assigned, and for the purposes of energy estimation during the synthesis process the static method based on probabilistic properties of input signals is used. The synthesis is comprised of the technology independent phase where logic minimization and decomposition is performed on the Boolean functions equations and the technology dependent phase where mapping to a physical cell library is performed.