Title :
Impact of process variations on read failures in SRAMs
Author :
Harutyunyan, G. ; Shoukourian, S. ; Vardanian, V. ; Zorian, Y.
Abstract :
In this paper we have analyzed failures caused by process variations in Static Random Access Memories (SRAMs). The validation for read failures is done using SPICE simulations for a 28 nm SRAM cell, as well as the worst corner cases (voltage, temperature, frequency) for their testing are identified. The functional fault models corresponding to process variation failures are considered and minimal test algorithms for their detection are proposed.
Keywords :
SRAM chips; failure analysis; integrated circuit reliability; integrated circuit testing; SPICE simulations; SRAM cell; functional fault models; minimal test algorithms; process variation ipact; read failures; size 28 nm; static random access memory;
Conference_Titel :
Design & Test Symposium, 2013 East-West
Conference_Location :
Rostov-on-Don
Print_ISBN :
978-1-4799-2095-2
DOI :
10.1109/EWDTS.2013.6673115
