Test data compression strategy while using hybrid-BIST methodology

In this paper a strategy is proposed for compressing the test data while using concurrent hybrid-BIST methodologyfor testing SoCs. In the proposed method, in addition tousing BIST strategy for testing cores with deterministic sequential test patterns in an SoC( Without using scan chains), (ATE) is used for testing cores with deterministic test patterns through Test Access Mechanism (TAM) or functional bus. As will be shown in experimental results, this process compresses hybrid-BIST overall test patterns considerably that affects the overall Test Application Time (TAT) in comparison with pure deterministic, pure pseudo random, and combination of deterministic and pseudo random test patterns.