DocumentCode
648600
Title
Architecture of built-in self-test and recovery memory chips
Author
Andrienko, V.A. ; Diaa, Moamar ; Ryabtsev, V.G. ; Utkina, T.Yu.
Author_Institution
Cherkassy State Technol. Univ., Cherkasy, Ukraine
fYear
2013
fDate
27-30 Sept. 2013
Firstpage
1
Lastpage
12
Abstract
The article is devoted to increasing the coefficient of technical readiness of memory chips. The architecture of built-in self-test and repair is proposed, what allows changing a bit data of the primary array of memory cells, in which the failure is occurred, on the data coming from the outputs of an array of backup memory cells. The proposed hardware and software provide automatic reconfiguration of the data upon failure of chip.
Keywords
built-in self test; failure analysis; integrated circuit testing; random-access storage; automatic reconfiguration; backup memory cell array; built-in self-test architecture; chip failure detection; recovery memory chip architecture;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium, 2013 East-West
Conference_Location
Rostov-on-Don
Print_ISBN
978-1-4799-2095-2
Type
conf
DOI
10.1109/EWDTS.2013.6673185
Filename
6673185
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