DocumentCode :
648652
Title :
Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs
Author :
Adel, Heike ; Louerat, Marie-Minerve ; Sabut, Marc
Author_Institution :
LIP6 Lab., Pierre & Marie Curie Univ., France
fYear :
2013
fDate :
7-9 Oct. 2013
Firstpage :
23
Lastpage :
26
Abstract :
The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; integrated circuit design; CMOS; MDAC; digitally calibrated pipelined ADC; gain error correction; low gain amplifier; multiplying analog-to-digital converter; size 40 nm; word length 12 bit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location :
Istanbul
Type :
conf
DOI :
10.1109/VLSI-SoC.2013.6673239
Filename :
6673239
Link To Document :
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