DocumentCode
648653
Title
A real-time 720p feature extraction core based on Semantic Kernels Binarized
Author
Schaffner, Michael ; Hager, Pascal ; Cavigelli, Lukas ; Greisen, Pierre ; Gurkaynak, Frank K. ; Kaeslin, Hubert
Author_Institution
ETH Zurich, Zurich, Switzerland
fYear
2013
fDate
7-9 Oct. 2013
Firstpage
27
Lastpage
32
Abstract
Several image processing applications rely on a sparse set of correspondence points between stereo images to discern a sparse but robust depth structure of the scene. There exist several methods to extract and match correspondences, but they are all computationally extensive and require significant memory bandwidths. In this paper, we describe an efficient ASIC core that is able to detect up to 25 k interest points in real time on a 720p video stream using the recently proposed Semantic Kernels Binarized (SKB) algorithm. To keep the memory bandwidth low, an optimized method to calculate the filter responses in the interest point detection stage has been devised. Instead of the 2D integral image we use a local 1D integral image combined with an incremental updating scheme to calculate the box filters. The ASIC core is manufactured in 180 nm technology and has a complexity of 254 kGE. It runs at 100 MHz, has a power dissipation of 184 mW and is the central processing block for a larger FPGA based stereo vision system that calculates a sparse depth map by locating corresponding interest points between left and right images in real time.
Keywords
application specific integrated circuits; feature extraction; field programmable gate arrays; filtering theory; integral equations; object detection; stereo image processing; video streaming; ASIC core; FPGA; SKB algorithm; box filters; central processing block; correspondence points; filter responses; frequency 100 MHz; image processing applications; incremental updating scheme; interest points detection; local 1D integral image; memory bandwidth; power 184 mW; power dissipation; real-time feature extraction core; semantic kernels binarized algorithm; size 180 nm; sparse depth map; stereo images; stereo vision system; video stream;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location
Istanbul
Type
conf
DOI
10.1109/VLSI-SoC.2013.6673240
Filename
6673240
Link To Document