Title :
Power-aware SoC test optimization through dynamic voltage and frequency scaling
Author :
Sheshadri, Vijay ; Agrawal, Vishwani D. ; Agrawal, Pulin
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
Reducing test cost by minimizing the overall test time remains one of the main goals of System-on-Chip (SoC) testing. Power-aware strategies optimize the overall test time of a SoC for a global peak power budget. Test time and test power can be regulated by VDD and test clock frequency to optimize SoC test schedules for a given power budget. Dynamic voltage and frequency scaling (DVFS) techniques have been used in the past to optimize energy efficiency in SoCs. In this paper, we extend the concept of DVFS to optimize the test scheduling of SoC. We adopt a sessionless test scheduling strategy and provide a simple heuristic approach for its optimization. The proposed idea is implemented on several ITC02 benchmarks. Results show significant test time reduction over sessionless reference test schedules for which VDD and clock frequency are fixed at nominal values.
Keywords :
energy conservation; integrated circuit testing; optimisation; power aware computing; system-on-chip; DVFS techniques; SoC test schedules; SoC testing; dynamic voltage; energy efficiency; frequency scaling; global peak power budget; power-aware SoC test optimization; power-aware strategy; sessionless test scheduling strategy; system-on-chip testing; test clock frequency; test cost reduction; test time reduction;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location :
Istanbul
DOI :
10.1109/VLSI-SoC.2013.6673258
