Title :
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology
Author :
Pelloux-Prayer, B. ; Valentian, Alexandre ; Giraud, Bastien ; Thonnart, Yvain ; Noel, Jean-Philippe ; Flatresse, Philippe ; Beigne, Edith
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two candidate technologies for replacing Bulk technology at sub-20 nm nodes. Although it represents a smooth transition from Bulk, i.e. being a planar technology with a similar gate stack and a simpler front-end-of-line process, it enables a reinforced process-design co-optimization thanks to Well engineering capability. This added degree of freedom has unleashed the creativity of designers and technologists, creating objects like `flip-Well´ and `single-Well´ logic gates. This paper presents the state-of-the-art of UTBB FD-SOI implementation strategies and solves the multi-VT constrains thanks to innovative fine grain co-integration approaches.
Keywords :
flip-flops; logic gates; silicon-on-insulator; UTBB FD-SOI technology; fine grain multivoltage cointegration methodology; flip-well logic gates; front-end-of-line process; gate stack; reinforced process-design cooptimization; single-well logic gates; ultrathin body-box fully-depleted SOI technology; FD-SOI; Ultra-Thin Body and BOX; energy efficiency; low voltage; multi-VT;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location :
Istanbul
DOI :
10.1109/VLSI-SoC.2013.6673270