Low cost FPGA design and implementation of a stereo matching system for 3D-TV applications

There exist numerous solutions to the stereo matching problem and many have been implemented on FPGAs. However, these solutions are conceived and designed as a stand-alone module without considering the area constraints and hard deadlines of the underlying application. In this paper, we propose a low-cost and real-time stereo matching system that is specifically designed to be integrated into the video pipeline of a Full-HD 3D-TV system, which is compliant with HDMI 1.4a specification. The proposed hardware architecture was implemented in VHDL and mapped on low-cost Spartan6-XC6SLX9 FPGA. The implementation runs at 148.5 MHz and achieves 60 fps in order to meet the HDMI 1.4a requirements, while using only 3k LUTs and 29 of 16Kb-BRAMs. Compared to existing work, the proposed implementation can generate high quality disparity maps with a much compact implementation. Moreover, to the best of our best knowledge, we present the first hardware implementation of information permeability based stereo matching algorithm, which exploits one of the most efficient aggregation methodologies compared to the state-of-the-art. We also identify the problems brought out during the system level integration and provide novel solutions to them.