A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

Aggressive technology scaling has led to a significant reduction of device reliability. As a consequence Integrated Circuits (ICs) reliability became a major issue and Dynamic Reliability Management (DRM) schemes have been proposed to assure ICs´ lifetime reliability. Though, up to date, various aging sensors have been proposed, few of them can provide real quantitative aging measurements. In view of this, we propose a direct measuring scheme by using the drain current as aging indicator. We designed a novel on-chip aging sensor able to detect the amalgamated aging effects of ICs caused by joint failure mechanisms. This is achieved by detecting the peak power supply current (I_pp) degradation from the device and/or circuit, which is a signature of the total drain current. Unlike the existing aging sensors which indirectly estimate the aging status of a device, the proposed sensor allows for direct aging assessment for single device and/or circuit blocks. Simulation results using the TSMC 65nm technology indicate that the proposed sensor can operate at 1GHz. Accelerated test simulation in Cadence for a set of ISCAS85 benchmark circuits indicates that the drain current exhibits a similar aging rate as the threshold voltage for the entire circuit lifetime, but with a better sensitivity towards the End-of-Life (EOL), which demonstrates the validity and practical relevance of the proposed aging monitoring framework.