A power-efficient hierarchical network-on-chip topology for stacked 3D ICs

Multi-Processors Systems-on-Chip (MPSoCs) are demanding for high performance, low power and high density, and therefore, three-dimensional integrated circuits (3DIC) emerge as a solution to integrate these systems. In order to appropriately interconnect the layers of these systems in terms of flexibility and scalability, a Network-on-Chip (NoC) is typically employed. In this paper, we argue about the scenario of 3D designs, covering all important issues about this new concept. In agreement with all features discussed in this paper, we have proposed a hierarchical 3D topology that meets well the reality of these designs. Experimental results analyze different topologies and show the large benefits in area and power of our proposal.