Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC

Author

Yajuan He ; Bo Chen ; Qiang Li

Author_Institution

Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2013

fDate

7-9 Oct. 2013

Firstpage

348

Lastpage

351

Abstract

A 14-bit and 200-MS/s SHA-less pipelined ADC is implemented by 0.13 μm CMOS process with blind least mean square (BLMS) calibration technique which corrects errors of this pipelined ADC with fast, low gain and inaccurate opamps. Using skip and fill approach, we employ an interpolation filter and a front-end DAC to make the pipelined ADC self-calibratable in the background. Incorporated a 18 stages and 1.5 bit/stage structure, the simulation shows the ADC achieves an SINAD of 86 dB, an SFDR of 107 dB with a 90.55 MHz input signal.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; calibration; digital-analogue conversion; filters; least mean squares methods; CMOS process; SHA-less pipelined ADC; blind least mean square calibration technique; blind-LMS based digital background calibration; error correction; frequency 90.55 MHz; front-end DAC; interpolation filter; opamps; size 0.13 mum; skip-fill approach; word length 14 bit; BLMS background calibration; analog-digital-mixed chip; nonlinearity correction; pipelined ADC; skip and fill;

fLanguage

English

Publisher

ieee

Conference_Titel

Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on

Conference_Location

Istanbul

Type

conf

DOI

10.1109/VLSI-SoC.2013.6673307

Filename

6673307