Analog-to-digital converters power dissipation limits of CBSC-based pipelined

The comparator-based switched-capacitor (CBSC) technique has been used in low power analog to digital converters (ADCs). The objective of this paper is to derive the theoretical power bound for CBSC-based pipelined ADCs with digital error correction (1.5 bit/stage). To achieve this, the constituent building blocks whose performance is limited by noise, are examined to derive the power bound. The optimum values of design parameters influencing the power bound are also investigated including the optimal output ramp rates needed to achieve a given linearity constraint, comparator bias current and delay time. The accuracy of the derived equations is verified through behavioral simulation in MATLAB.