• DocumentCode
    648727
  • Title

    A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters

  • Author

    Chien-Hung Kuo ; Cin-De Jhang

  • Author_Institution
    Dept. Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei, Taiwan
  • fYear
    2013
  • fDate
    7-9 Oct. 2013
  • Firstpage
    386
  • Lastpage
    389
  • Abstract
    This paper presents a center-aligned hybrid digital pulse-width modulator for the envelope modulation of polar transmitters [1]. To obtain better noise figure of the outputs, a 128-phase delay-locked loop is used to generate center-aligned output pulses having 64 different pulse widths for 6-bit signal input. To reduce the number of delay cells in the multi-phase DLL, a simple counter is used to separate the output phases of DLL into rise and fall parts. The proposed digital pulse-width modulator is simulated in TSMC 90nm 1P9M process. The power consumption is 0.85 mW at a 92.16 MHz input reference frequency and a supply voltage of 1.2V.
  • Keywords
    delay lock loops; power consumption; pulse width modulation; radio transmitters; TSMC; center-aligned digital pulsewidth modulator; center-aligned hybrid digital pulse-width modulator; center-aligned output pulses; delay cells; envelope modulation; frequency 92.16 MHz; input reference frequency; multiphase DLL; noise figure; output phases; phase delay-locked loop; polar transmitters; power 0.85 mW; power consumption; pulse widths; supply voltage; voltage 1.2 V; DPWM; Envelope modulation; LTE polar modulation transmitter;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
  • Conference_Location
    Istanbul
  • Type

    conf

  • DOI
    10.1109/VLSI-SoC.2013.6673314
  • Filename
    6673314