Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

Author

Nayak, Kaushik ; Agarwal, Sankalp ; Bajaj, Mohit ; Oldiges, Philip J. ; Murali, Kota V. R. M. ; Rao, Valipe Ramgopal

Author_Institution

Dept. of Electr. Eng., IIT Bombay, Mumbai, India

Volume

61

Issue

11

fYear

2014

fDate

Nov. 2014

Firstpage

3892

Lastpage

3895

Abstract

The metal-gate granularity-induced threshold voltage (V_T) variability and V_T mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode V_T variability are analyzed. The V_T mismatch study predicts lower mismatch figure of merit (A_VT) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs.

Keywords

MOSFET; elemental semiconductors; nanowires; silicon; statistical analysis; titanium compounds; GAA n-NWFET; Si; TiN; coupled 3D statistical device simulations; figure of merit; gate-all-around nanowire n-MOSFET; linear mode; metal-gate crystal grain size; metal-gate granularity-induced threshold voltage variability; quantum corrected room temperature drift-diffusion transport; saturation mode; temperature 293 K to 298 K; FinFETs; Grain size; Logic gates; Nanoscale devices; Silicon; Gate-all-around (GAA); metal-gate granularity (MGG); mismatch; silicon nanowire FET; threshold voltage; variability; work function (WF);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2351401

Filename

6895292