A new VLSI architecture for 3D-DCT video compression system

The three-dimensional discrete cosine transform (3D-DCT) has been researched as an alternative to existing dominant video standards based on motion estimation and compensation. However, so far no definitive research has been done on its efficient architecture and implementation. Previous research results have presented simple architectures prototyped directly from theory, which have critical deficiencies in terms of timing and size. This paper proposes a novel and practical VLSI architecture for 4×4×4 3D DCT/IDCT to overcome those deficiencies. To meet latency and throughput requirements for pipelining, we apply a specific architecture well-fitted for each stage. Proposed architecture is designed to take 75 percent of frame memory compared with all other video systems such as MPEG-2/4, H.263(+), and other 3D-DCT systems. As a simulation result, performance degradation compared with theoretical analysis is about PSNR 0.02 dB small enough to ignore. To lower size and power, arithmetic modules are simplified while meeting its target performance.