DocumentCode :
649127
Title :
Hardware and software design for QR Decomposition Recursive Least Square algorithm
Author :
Sufeng Niu ; Sizhou Wang ; Aslan, S. ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
117
Lastpage :
120
Abstract :
In this paper, an embedded hardware and software system design and implementation for QR Decomposition Recursive Least Square (QRD-RLS) algorithm using Givens Rotation are presented. Furthermore, hardware and software design optimization are introduced to the Givens Rotation-based method. The computation performance is compared for hardware implementation running on Xilinx Virtex-5 FPGA, and software design running on two different processors (Intel i7 processor and ARM embedded processor) for solving least square problems. The challenges for hardware optimization and software algorithm are also presented.
Keywords :
field programmable gate arrays; hardware-software codesign; least squares approximations; optimisation; ARM embedded processor; Intel i7 processor; QR decomposition recursive least square algorithm; QRD-RLS algorithm; Xilinx Virtex-5 FPGA; hardware design optimization; software design optimization; Least square problem; QR decomposition; RLS; hardware and software; systolic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674599
Filename :
6674599
Link To Document :
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