DocumentCode
649154
Title
Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC sample clock synthesis
Author
McNeill, John A. ; Jianping Gong ; Majidi, Rabeeh
Author_Institution
Electr. & Comput. Eng. Dept., Worcester Polytech. Inst., Worcester, MA, USA
fYear
2013
fDate
4-7 Aug. 2013
Firstpage
225
Lastpage
228
Abstract
This paper presents a design technique for generation of GHz ADC sampling clock phases from a low-cost low-frequency clock source. Jitter of order 0.1ps is enabled using a DLL-based frequency multiplication method. Nonidealities of the DLL approach are mitigated through digital background correction. Simulated results in a 180nm CMOS process are presented.
Keywords
CMOS integrated circuits; analogue-digital conversion; delay lock loops; frequency multipliers; jitter; ADC sample clock synthesis; ADC sampling clock phases; DLL-based frequency multiplication method; delay-lock-loop; digital background correction; low-cost low-frequency clock source; size 180 nm; sub-picosecond jitter;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location
Columbus, OH
ISSN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2013.6674626
Filename
6674626
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