DocumentCode :
649158
Title :
Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators
Author :
Hairong Chang ; Hua Tang
Author_Institution :
Qualcomm Inc., San Diego, CA, USA
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
245
Lastpage :
248
Abstract :
A recently proposed method to reduce clock jitter effects in continuous-time Delta-Sigma modulators is to generate a return-to-zero feedback with a fixed-width pulse for active feedback. In practice, the pulse width is subject to noise effects causing jitter of the pulse width itself. Therefore, jitter of the pulse width, though not the clock, may still degrade the performance of Delta-Sigma modulators. In this brief, we investigate practical feasibility of the method. It is shown that jitter of the pulse width could be conditionally much smaller than that of the clock, which therefore reduces clock jitter effects.
Keywords :
delta-sigma modulation; feedback; jitter; modulators; active feedback; clock jitter effects; continuous-time delta-sigma modulators; fixed-width pulse; fixed-width pulse RZ feedback; low-pass continuous-time δΣ modulators; noise effects; pulse width jitter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674631
Filename :
6674631
Link To Document :
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