High performance SAR ADC with offset and noise tolerance

This paper presents a modified offset and noise tolerant technique for successive approximation register (SAR) analog-to-digital converter (ADC). With the coarse comparator adopted in the first (n - m - 1) cycles and the fine comparator working in the rest (m + 2) cycles, the tolerance capability of this technique is ±2^mLSB. A prototype 10b 100MS/s SAR ADC with this technique is presented under 0.13μm CMOS technology. Voltage-Controlled-Delay-Line (VCDL) is adopted in the comparator to minimize offset, noise and power dissipation. At 1.2V supply and 100MS/s, the prototype SAR ADC achieves 9.56 bits effective-number-of-bit (ENOB) and consumes 1.66mW energy, resulting in a figure-of-merit (FoM) of 22fJ/conv.