Title :
A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS
Author :
Zhiliang Qiao ; Xiong Zhou ; Qiang Li
Author_Institution :
Centre for Commun. Circuits & Syst., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
An ultra-low-voltage switched-capacitor (SC) ΔΣ modulator operating at mere 0.25V supply voltage is presented. To facilitate noise shaping in subthreshold region, a novel two-stage inverter-based OTA with DC gain of 43dB is proposed. Also ultra-low-voltage switches and subthreshold comparator are exploited. The transistor-level simulation results show that with an oversampling ratio (OSR) of 64 and a sampling frequency (fs) of 1.28MHz under a 0.25V supply, the converter achieves 86.5dB SNDR over 10kHz bandwidth while consuming a total power of 33.8μW and yielding a figure of merit (FoM) of 97.8fJ/conversion-step.
Keywords :
CMOS digital integrated circuits; comparators (circuits); delta-sigma modulation; low-power electronics; operational amplifiers; switched capacitor networks; CMOS; DC gain; OSR; SNDR SC ΔΣ modulator; bandwidth 10 kHz; frequency 1.28 MHz; gain 43 dB; noise shaping; oversampling ratio; power 33.8 muW; sampling frequency; size 0.13 mum; subthreshold comparator; subthreshold region; transistor-level simulation; two-stage inverter-based OTA; ultralow-voltage switched-capacitor ΔΣ modulator; voltage 0.25 V;
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
DOI :
10.1109/MWSCAS.2013.6674635
