A Winner-Take-All circuit with improved accuracy and tolerance to mismatch and process variations

Winner-Take- All (WTA) circuit chooses a winner input from a set of input signals. WTA circuits employ transistors that operate in the sub-threshold or weak inversion region. With technology scaling, sub-threshold circuits are prone to mismatch and process variations which degrade the performance of these circuits. This paper presents a novel WTA circuit that employs a CMOS double pair transistor as a translinear element that is more tolerant to mismatch and process variations. Monte Carlo simulations are used to compare the performance of the existing and the proposed topologies to estimate the effects of process and mismatch variations. Results show that the proposed circuit is able to reduce the range of variations by three orders of magnitude compared to original one for similar variations in the transistor parameters. The proposed element also shows better accuracy in replicating the maximum input current compared to the original circuit.