Elimination of false codes in an asynchronous parallel successive approximation A/D converter

We report on a scheme to eliminate false codes generated due to switching delays among the output bits of an asynchronous parallel successive approximation analog-to-digital converter (SA-ADC) developed by Lin and Liu [1]. False output codes are eliminated by converting the binary outputs to Gray codes. A novel asynchronous parallel gray-to-binary converter is introduced to effectively reduce switching delays from 10.0 - 26.5 ns to 767 - 962 ps, when operating with a 50 kHz triangular input and 2V power supply. Simulated INL and DNL are less than ± 0.4 LSB and ± 0.45 LSB, respectively, at 800 μW of power consumption. Measurement results of the ADC, fabricated in 0.5-μm CMOS technology, show the efficacy of the proposed scheme to remove false codes.