Fast statistical process variation analysis using universal Kriging metamodeling: A PLL example

The design of Analog Mixed-Signal Systems-on-Chip (AMS-SoCs) presents difficult challenges given the number of design specifications that must be met. This situation is more aggravating in the presence of process variation effects for nanoscale technologies. Existing statistical techniques heavily rely on Monte-Carlo analysis for design parameters in an effort to mitigate the effects of process variation. Such methods, while accurate are often expensive and require extensive amount of simulations. In this paper we present a geostatistical based metamodeling technique that can accurately take into account process variation and considerably reduces the amount of time for simulation. An illustration of the proposed technique is shown using a 180nm PLL design. The proposed technique achieves an accuracy of 0.7 % and 0.33% for power consumption and locking time, respectively, and improves the run time by about 10 times.