Spatio-temporal tunable pixels for multi-spectral infrared imagers

In this paper, a new 96 × 96 30 μm pitch mixed-signal readout integrated circuit (ROIC) with a pixel-level tunable bias control is demonstrated. The new ROIC is capable of providing a large bias voltage in both polarities on each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. In addition to the VLSI development, an FPGA-based testbench has been developed to test and characterize the new ROIC system. The unit cell consists of the CTIA integrator, two analog memories, one address selector, and one reference recover switch, built with 15 transistors and 3 capacitors. The test chip has been fabricated in 2P4M 0.35 μm high-voltage CMOS technology, where the bias voltage range is +/-5V and the output voltage swing is +/-3.9 V.