Near-threshold CNTFET SRAM cell design with gated cell power supply

In this paper we report an in-depth study of power supply reduction towards near-threshold for an 8-transistor CNTFET SRAM cell. Near-threshold voltage provides savings in power consumption, but has negative impact on delays, noise margin and yield. We have incorporated a removed metallic CNT approach to deal with non-semiconductor CNTs. Monte Carlo simulations have shown that with Vdd down to 0.5V, 0.72% of the cells are non-functional after removing the metallic CNTs. The power saving is over 5X, while the average delay is increased by 3.5X as compared to 0.9V Vdd. To further improve yield and performance, the gated cell power supply technique is applied which weakens the pull-up transistors during write and effectively eliminates all the write failures at near-threshold voltage level. At Vdd=0.5V, the cell with gated power supply improves write performance and write EDP by 1.5X and 2.9X compared to the non-gated cell. It also saves 70% total energy and achieves 38% lower EDP than a cell at nominal Vdd (0.9V).