CMOS photovoltaic-cell layout configurations for harvesting microsystems

Wireless microsensors add intelligence to otherwise inaccessible locations and large infrastructures, such as tiny crevices in hospitals, factories, and farms. These small devices, however, store little energy, so functionality is low or lifetime is short, or both. Luckily, harnessing ambient energy can replenish these microsystems, and because solar light generates considerably higher power density than motion, temperature, and radiation, photovoltaic (PV) systems are appealing options. Still, chip-sized CMOS PV cells produce only microwatts, and power-conditioning circuits consume some of that, leaving little energy for the sensor system. In view of this constraint, this paper shows that a 0.18-μm CMOS system is 6% more efficient with four stacked 1-mm² PV cells than with one 4-mm² cell. However, stacking P⁺-N Well cells, which is the only stackable PV structure, is 20% less efficient than one cell, so systems that draw power from one N⁺ or N well in substrate cell are better.