Title :
Novel clock gating techniques for low power flip-flops and its applications
Author :
Shaker, Matineh ; Bayoumi, M.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA, USA
Abstract :
Two new clock gated flip-flops are presented. The designs are based on new clock gating approaches to reduce the consumption of clock signal´s switching power. They operate with no redundant clock cycles and have reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flops are used to design 8-bit successive approximation register. This application has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using Spectre. Simulations with the inclusion of parasitics have shown the effectiveness of the new approaches on power consumption and transistor count.
Keywords :
CMOS digital integrated circuits; clocks; flip-flops; integrated circuit design; low-power electronics; CMOS technology; Spectre; clock gating techniques; data signals; low power flip-flops; power consumption; size 90 nm; successive approximation register design; switching activity; transistor count; voltage 1 V; word length 8 bit; clock gating; flip-flop; switching activity;
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
DOI :
10.1109/MWSCAS.2013.6674675