Low-power content-addressable memory design using a double match-line (DML) architecture

Content addressable memory (CAM) is a fast lookup hardware table. However, its parallel comparison feature and frequent lookup cause significant power consumption. In this paper we propose a low power match-line architecture, called double match-line (DML) design, in which we combine the charge sharing and segmentation technique to largely reduce the CAM power dissipated in the ML switching activity. Unlike the conventional CAM design, where only a single ML is used, our design uses two MLs to perform the search operation. By reducing the ML swing, our design can minimize the charge loss in the search operation. Based on TSMC 90nm technology, the simulation results show that our design can reduce the search energy consumption of the CAM by 84% at most compared to the conventional NOR-type CAM design.